Recent computer systems require faster microprocessors. These computer systems which require fast microprocessors require high memory bandwidth and high memory component capacity. This is particularly true in systems that contain multiple fast microprocessors.
In order to meet the demands of systems containing multiple fast microprocessors, some recent prior art memory modules include up to eighteen memory components on each memory module. These memory systems typically use Dual Inline Memory Modules (DIMMs) aligned in parallel. Typically, each DIMM includes memory components that are Dynamic Random Access Memory (DRAM) semiconductor devices or Synchronous Dynamic Random Access Memory (SDRAM) devices. At slower speeds, these prior art memory modules function adequately. However, at speeds of 200 megahertz and more, signal distortion occurs. This signal distortion causes ringing and edge rate slowdown. In some cases, the signal distortion results in insufficient signal to transfer data.
Recent attempts to meet the demands of systems containing multiple fast microprocessors include architectures that use data switching. Such systems include Field Effect Transistors (FET) devices that operate as switches located on each memory module. These FET switches, in effect, switch off individual memory modules such that only one or two memory modules are transmitting data at any one time. This significantly reduces signal distortion.
Memory modules that include FET switches located on each memory module are effective in reducing signal distortion. However, such memory modules are large and are expensive to manufacture. The inclusion of multiple FET switches adds cost and increases the required size of each memory module. Also, the connection scheme is complicated by the need to couple each data line to one or more FET. This results in a memory module that is complex and that is expensive to manufacture.
Prior art memory modules typically include terminal resistors located on each memory module. These terminal resistors couple to each data line. The terminal resistors take up valuable space on each memory module. Also, the terminal resistors increase the manufacturing cost of the memory module. In addition, such prior art memory modules typically include Series Stub Termination Logic (SSTL) which takes up valuable space on each memory module and increases the manufacturing cost of the memory module.
What is needed is a memory system that has a high memory component capacity and a high data bandwidth while minimizing distortion. Also, a memory system is needed that meets the above requirements and that includes a memory module that is inexpensive to manufacture. In addition, a memory system is needed that meets the above requirements and that includes a memory module that is smaller than prior art memory modules that include FET switches. The present invention provides an elegant solution to the above needs.